1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device and more particularly to a method of manufacturing a semiconductor device which has a salicide (self-aligned-silicide) process.
2. Description of the Prior Art
In the art of semiconductor devices, there have been, at all times, demands to achieve higher integration and further miniaturization. On the other hand, when the gate length of MOSFET (Metal-Oxide-Semiconductor Field Effect Transistor) becomes equal to or less than 0.35 .mu.m or so, problems such as a short channel effect take place. If diffusion layers are made thin to suppress the short channel effect, the resistance of diffusion layers increases. Accordingly, to overcome these problems, there has been being tried the application of a salicide process wherein a cobalt film is grown on the surfaces of a source layer, a drain layer and polysilicon forming a gate electrode, and then cobalt silicide is formed by heating and thereby the resistance thereof is lowered.
However, as shown in FIG. 6, from a bottom section of a cobalt silicide layer formed on the surface of a source layer 9 and a drain layer 10 on a silicon substrate 1, cobalt silicide may grow abnormally in the form of spikes and pierce through the source layer 9 and the drain layer 10, both of which are formed thin with a thickness of 100 nm or so, and cause a problem of the leakage current.
In order to solve such a problem, Japanese Patent Application Laid-open No. 251967/1997 discloses a method of lowering the resistance. In this method, prior to the formation of a cobalt film, an amorphous layer is first formed in the upper section of an impurity diffusion layer on a silicon substrate by ion implantation, and then a cobalt film is formed over the impurity diffusion layer. Next, the cobalt film and silicon within the impurity diffusion layer are made to react each other by a first heat treatment at a relatively low temperature and, as a result, a cobalt silicide layer comprising CoSi or Co.sub.2 Si is formed in the upper section of the amorphous layer. Following this, the unreacted cobalt is removed and then a second heat treatment is performed so as to turn CoSi or Co.sub.2 Si into CoSi.sub.2, and, thereby, to lower the resistance.
According to this disclosure, the amorphous layer prevents the constitutive elements of the cobalt silicide from moving downwards so that the generation of spikes can be suppressed.
However, in this method, it is difficult to control the conditions in such a way that the amorphous part is completely consumed. A part of amorphous tends to remain as lattice defects between the cobalt silicide layer and the source-drain layer, which leads to problems such as deterioration of transistor characteristics including the ON-current, and lowering of the reliability. While the amorphous part left as defects can be restored by annealing at high temperature, the temperature required for that normally exceeds 900.degree. C. This causes the aggregation of cobalt silicide and lowers the heat resistance of the cobalt silicide film and, further, makes the electric resistance high again.